1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming planarized shallow trench isolation (STI) in the fabrication of integrated circuits.
2. Description of the Prior Art
As device technology is scaled down to the quarter micron regime, the use of the conventional local oxidation of silicon (LOCOS) isolation will be confined by smaller channel-width encroachment (bird's beak). Shallow trench isolation (STI) can be used to eliminate these encroachments, especially in ultra large scale integrated (ULSI) circuit devices. To achieve good planarity after STI, chemical mechanical polishing (CMP) is often used. However, due to pad deformation, the trench open area is susceptible to dishing which causes oxide thinning in the wide trench.
A number of workers in the art have addressed the CMP planarization issue. U.S. Pat. No. 4,962,064 to Haskell et al and the prior art of U.S. Pat. No. 5,721,173 to Yano et al teach the use of a polysilicon hard mask layer in planarizing shallow trench isolation (STI). U.S. Pat. No. 5,356,513 to Burke et al uses a series of alternating "hard" and "soft" polishing layers for planarizing an oxide layer over a metal pattern. U.S. Pat. No. 5,290,396 to Schoenborn et al and U.S. Pat. No. 5,441,094 to Pasch disclose a silicon nitride hard mask and a one-step CMP process. U.S. Pat. No. 5,575,886 to Murase shows a global planarization process using CMP.